There has been known a Magnetic Tunnel Junction (MTJ) that is a magnetoresistive element.
As depicted in FIG. 1, the MTJ is an element that includes two layers exhibiting magnetism and a barrier layer provided between the two layers.
Furthermore, as depicted in FIG. 2, a resistance of the MTJ can be changed depending on a voltage applied to the MTJ. Owing to this, it is possible to store information in the MTJ in such a manner, for example, that “1” is stored to correspond to a high resistance state and “0” is stored to correspond to a low resistance state. In FIG. 2, a horizontal axis indicates the voltage and a vertical axis indicates the resistance.
It is assumed herein that the low resistance state of the MTJ is referred to as “Parallel state” (hereinafter, also referred to as “P state”) and that the high resistance state thereof is referred to as “Anti-Parallel state” (hereinafter, also referred to as “AP state”).
The information stored in the MTJ is retained even if a power is interrupted. Therefore, data in a volatile memory circuit is written to and stored in the MTJ (hereinafter, this operation is also referred to as “store operation”) before power gating (PG) interrupts power of the circuit and the power is then interrupted. After power return, the data stored in the MTJ is read out to the volatile memory circuit (hereinafter, this operation is also referred to as “restore operation”) and an operation is restarted.
Now, FIG. 3 depicts a circuit configuration of a non-volatile flip-flop (NVFF) using such MTJ elements. This circuit configuration is an example in which a pMOS (positive Metal Oxide Semiconductor) transistor is employed as a power switch (PS) that is used for power interruption at a time of implementing the PG.
A power supply line of the NVFF circuit is connected to a virtual power supply line (VDDV) and coupled to a true power supply line VDD via the PS configured with the pMOS transistor. With this configuration, when the PS is turned off, power of the NVFF circuit is interrupted. A control signal RB is an asynchronous reset signal, so that data stored in the NVFF can be initialized to “0” by setting the control signal RB to “0.”
The NVFF circuit sets a control signal SR to “1,” turns on an nMOS connected to the control signal SR, and applies voltages corresponding to both “1” and “0” to a control signal CTRL, thereby writing retained 1-bit information to the MTJs. Furthermore, the NVFF circuit turns on the control signal SR and the PS after the PG, whereby a circuit state of the NVFF circuit returns to a state of having written data by using a resistance difference between the MTJs. This restore operation uses the following phenomenon.
In a case of the power gating using the pMOS transistor as the PS, voltages of nodes within the circuit decrease to be close to 0 V by leakage with passage of time after the PG. When the NVFF circuit turns on the control signal SR and the PS and sets the CTRL to 0 V at a time of the power return, a restore current is carried from a slave latch to which a power supply voltage is supplied to the CTRL line through magnetoresistive elements MTJ1 and MTJ2.
If the magnetoresistive element MTJ1 is in a high resistance state and the magnetoresistive element MTJ2 is in a low resistance state, a voltage of a node N3 increases to be higher than a voltage of a node N4 when the restore current is carried. Owing to this, a conductance reduction due to an increase of a source voltage occurs in an nMOS transistor TR1 more conspicuously than in an nMOS transistor TR2.
The current carried through the nMOS transistor TR1 thereby becomes lower than that carried through the nMOS transistor TR2 and a current difference between the transistors TR1 and TR2 is equal to or greater than the resistance difference between the magnetoresistive elements MTJ1 and MTJ2. As a result, a voltage of a node N1 increases to be higher than a voltage of a node N2, a positive feedback is applied in a loop configured with an INV1 and a NAND (Not AND) within the slave latch, and the voltage of the node N1 returns to a power supply voltage, that is, the value “1” and the voltage of the node N2 returns to 0 V, that is, the value “0.”
In this way, the existing circuit generates the current difference equal to or greater than the resistance difference between the magnetoresistive elements MTJ1 and MTJ2 by using the conductance reduction due to the increase of the source voltage during the restore operation by using the nMOS transistor for each of the TR1 and TR2 in implementing the power gating using the pMOS transistor as the PS, thereby realizing the stable restore operation.
As described above, the flip-flop depicted in FIG. 3 can continue to retain the data (exhibit non-volatility) even with the power interruption.
Furthermore, when a circuit including the NVDFF (Non-volatile D Flip-Flop) is in a standby state, implementing the PG can greatly suppress unnecessary energy from being consumed during standby. Moreover, it is possible to retain the circuit state before and after the implementation of the PG.